Processors (e.g., microprocessors) are well known and used in a wide variety of products and applications, from desktop computers to portable electronic devices, such as cellular phones and PDAs (personal digital assistants). As is known, some processors are extremely powerful (e.g., processors in high-end computer workstations), while other processors have a simpler design, for lower-end, less expensive applications and products.
As is also known, there is a general dichotomy between performance and power. Generally speaking, high-performance processors having faster operation and/or more complex designs tend to consume more power than lower-performance counterparts. Higher power consumption generally leads to higher operating temperatures and shorter battery life (for devices that operate from battery power). The ever-increasing demand and use of portable electronic devices is driving a demand to produce processors that realize lower-power operation, while at the same time maintaining satisfactory performance levels.
One known way of reducing the power consumption of devices is to provide modes of low-power operation (sometimes referred to as “sleep states”) when the devices (or certain portions thereof) are not in use. However, there is also a desire to reduce the power consumption of devices, during active operation. This is often accomplished by providing more efficient designs to the operational components of the devices.
There are a number of power-consuming components in various electronic devices, and the processor is one of them. Even within a processor, there are a variety of functional sections, and decode logic is one such area. As is known, the decoder logic of a processor decodes an encoded instruction into a number electrical signals for controlling and carrying out the function of the instruction within execution logic provided on in the processor. FIG. 1 is a block diagram illustrating conventional decode logic within a processor.
At a very high level, the fetch/execute portion 10 of a processor includes fetch logic 12 for fetching an encoded instruction and decoder logic 14 for decoding the instruction. As mentioned above, the decoder 14 operates to decode an encoded instruction into a plurality of signal lines 15, which are used to control and carry out the execution of the encoded instruction. In this regard, the outputs 15 from the decoder 14 are signal lines that are used as inputs and/or control signals for other circuit components within an execution unit (not shown) of the processor, and the execution unit carries out the functional operations specified by the encoded instructions. This basic operation is well known, and need not be described further herein.
In processors that accommodate more than one instruction set, or that accommodate instructions that are not contained within the instruction set that is accommodated by the decoder 14, logic 16 may be provided for performing a translation of an encoded instruction that would otherwise be unrecognized by the decoder 14. One way that such instructions have been handled in prior art systems is to provide logic 16 that translates the otherwise unrecognized instruction into a sequence of instructions that are recognized by the decoder 14. Of course, when processing a sequence of instructions, additional clock cycles are required for the decoding and execution of those instructions. FIG. 1 illustrates one way of structuring the circuitry for implementing such an approach.
As illustrated in FIG. 1, a multiplexer 18 may be used to selectively input to a decoder 14 either an instruction retrieved directly from the fetch logic 12, or one or more translated instructions received from the translation logic 16. Control logic 20 may be provided for selecting the multiplexer 18 input that is to be directed to the decoder 14. Generally, the control logic 20 would evaluate the encoded instruction received from the fetch logic 12 to ascertain whether it is an instruction that is recognizable by the decoder 14. If so, the multiplexer 18 would be controlled so as to direct the output from the fetch logic 12 to the decoder 14. If, however, the control logic 20 determines that the encoded instruction retrieved from the fetch logic 12 is not an instruction that is recognizable by the decoder 14, then the control logic 20 would control the multiplexer 18 to direct the output of the translation logic 16 to the decoder 14. Of course, additional implementation details would be needed, but are not described herein, as persons of ordinary skill in the art understand the relevant implementation details of the circuitry illustrated in FIG. 1.
Circuitry such as that illustrated in FIG. 1, however, has certain drawbacks. Specifically, the complexity and power requirements of the circuitry are excessive. It will be appreciated that a tradeoff exists between the complexity of the decoder 14 and the complexity of the translation logic 16. In this regard, as more instructions are accommodated by the circuitry of the decoder 14, then the decoder 14 becomes larger and more complex, and therefore more power-consuming. This is particularly disadvantageous when a number of the instructions are used only seldomly. Conversely, as the design of the decoder 14 becomes more simplified to accommodate fewer, more basic instructions, then additional logic will be provided in the translation logic 16 to accommodate additional instructions. Furthermore, while the translation logic 16 is active (actively translating otherwise unrecognized instructions), the decoder 14 is also powered and active to decode the instructions output from the translation logic 16. The simultaneous operation of both decoder 14 and translation logic 16 results in increased power usage.
Accordingly, what is desired is an improved decoder logic design for a processor realizing more efficient and lower-power operation.